1. Field of the Invention
The present invention relates to a circuit for generating a cyclic code for use in, for example, an encoding or scrambling apparatus.
2. Description of the Related Art
Cyclic codes are conventionally generated by a linear feedback shift register having a structure determined by a generator polynomial. As illustrated in FIG. 1 (for the generator polynomial Y=X4+X+1), the structure includes a plurality of register cells (R) 26, 27, 28, 29 and a logical exclusive OR (XOR) gate 30. A reset signal sets an initial value of “1” in register cell 29 and “0” in the other register cells 26, 27, 28.
The output of register cell 28 and the output of register cell 29, which is the output of the cyclic code generating circuit, are input to the exclusive OR gate 30 and XORed, and the result is sent to register cell 26. The register cells 26, 27, 28, 29 are interconnected to operate as a shift register driven by a clock signal (CLK). At the next pulse of the clock signal CLK, the existing values in register cells 26, 27, and 28 are stored in register cells 27, 28, and 29, respectively, and the XOR result is stored in register cell 26.
As a result, the contents of register cells 26, 27, 28 and 29 change from (0, 0, 0, 1) to (1, 0, 0, 0), from (1, 0, 0, 0) to (0, 1, 0, 0), from (0, 1, 0, 0) to (0, 0, 1, 0), and so on at successive clock pulses, and values of “1”, “0”, “0”, “0”, and so on are output as output data. The register cell contents at successive clock pulses are indicated in the vertical columns from LSB (least significant bit, register cell 26) to MSB (most significant bit, register cell 29) in FIG. 5, the output data being the content of the MSB column. The output data are XORed with data to be encoded or scrambled, generating encoded data or scrambled data.
Further information can be found in Japanese Patent Application Publication No. H5-344006.
When a cyclic code circuit with the structure described above is used, the output is serial: only one bit is output at each clock pulse. Accordingly, when the data to be encoded or scrambled are in parallel form, with multiple bits arriving at each clock pulse, the conventional cyclic code circuit requires a special high-frequency clock signal in order to output enough code bits to match the bit width of the input data.